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The ACCU passes on review copies of computer books to its members for them to review. The result is a large, high quality collection of book reviews by programmers, for programmers. Currently there are 1918 reviews in the database and more every month.
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Title:
High Performance Compilers for Parallel Computing
Author:
Michael Wolfe
ISBN:
0 8053 2730 4
Publisher:
Addison-Wesley
Pages:
570pp
Price:
£47-00
Reviewer:
Brian Bramer
Subject:
compilers; parallel systems
Appeared in:
10-5
Parallel hardware is becoming more common, however, the software to use such hardware lags far behind. For example, I have a four-processor system with FIFOs and shared memory for interprocessor communications but I still have to write separate C programs for each processor and the handle communications myself.

This book really deals with code generation for parallel systems. Chapter one considers matrix multiply and how performance can be improved on scaler processors by improving cache spatial or temporal locality (by changing loop order or structure) then moves on to consider improvements on vector, multi-processor (with shared memory), SIMD and MIMD architectures. Chapter two looks at language extensions to support parallelism, e.g. forall in High Performance Fortran. Chapters three and four deal with compiler analysis algorithms (graph concepts and linear algebra) and five to nine the optimiser (looking in particular at data dependence and how this effects scaler and parallel code generation). Code generation for a range of target architectures is then discussed, e.g. vector computers, shared memory parallel computers, message passing parallel computers, etc. Critical points considered are array references, generating concurrency from sequential and parallel loops (such as dopar and doall) and how nested loops are handled.

I found this a very interesting book relevant to my own research work. It would be useful not only for those writing compilers for parallel systems but also for anyone implementing code on sequential or parallel architectures who need to consider the efficiency of generated code (in particular loop generation and optimising array element access).